A packet switching network has switching points or nodes for transmission of data among senders and receivers connected to the network. The switching performed by these switching points is in fact the action of passing on packets or “frames” of data received by a switching point or node to a further node in the network. Such switching actions are the means by which communication data is moved through the packet switching network.
Each node may comprise a packet processor configured to process packets or frames of data. The packet processor may comprise a data storage unit, e.g., Double Data Rate Static Random Access Memory (DDR SRAM), configured with a plurality of buffers to store frame data. Each frame of data may be associated with a Frame Control Block (FCB) configured to describe the corresponding frame of data. Each FCB may be associated with one or more Buffer Control Blocks (BCBs) where each BCB associated with an FCB may be associated with a buffer in the data storage unit. A BCB may be configured to describe the associated buffer. Typically, FCBs and BCBs comprise various fields of information where the fields of information in FCBs and BCBs are each supplied by a separate memory, e.g., Quadruple Data Rate Static Random Access Memory (QDR SRAM), in the packet processor. That is, the fields of information in FCBs and BCBs may be obtained by accessing a separate memory, e.g., QDR SRAM, in the packet processor.
It would therefore be desirable to reduce the number of accesses to a particular memory, e.g., QDR SRAM, that supplies information to the fields of FCBs or BCBs thereby improving the efficiency of the bandwidth of the memory, e.g., QDR SRAM.